A Flexible Memory Block Recovering Strategy Using Mixed Error Control Techniques

Octavian Dumitru Mocanu, Joan Oliver

Abstract. This work presents a high qualitative reconfigurability method for fault-tolerant memories. It bases on a mixed technique of spare modules (cold spare), error correcting codes (Hamming SEC code), as well as electrical abnormal behaviour detectors (Iddq sensors). Complete reliability computations, which underlie the proposed scheme, search for a 99.90% tolerance to the cost of a small hardware overhead (2 spare (additional) 1K1 modules for each 1K16 of a memory system of 512K16, and Mean Time To Failure = 10-7 h-1). Finally, a CMOS implementation is envisaged. Complexity estimations show that the supplementary self-tolerance ensuring circuitry involves an overhead of 0.0094% for a 512K16 memory.
 
 

Key words. Analog detector, Digital test, Fault-tolerance, Memory system, Radiation-dependent failures
 
 

Registration: PIRDI-3/98, January 1998.


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